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“VLSI Design & Implementation of Transform & Quantization Module for Advanced Video Coding Standard H.264”.

This thesis describes the VLSI design & implementation of Integer Transform (IT) & quantization module for H.264/AVC. The design aims to provide significant complexity saving as well as adaptively controlling the computational complexity. Integer transform architecture is proposed for taking 4x4 pixels blocks of residual video data as an input. The integer transform is designed to remove the spatial redundancy in the video input which results in compression. The 4x4 integer transform is further reduced to two 2x2 sub-transforms. The two 2x2 matrix operations are performed in parallel thus satisfying the pipeline architecture which makes it more efficient. The multiplications in the transform operation are performed by simple left-shift operations while the division operation in the quantization process is achieved through right-shift operation. According to this design, 2-D transform is implemented by using duplicated l-D transform. It is shown that this architecture can flexibly control the computational complexity of each function with negligible loss of video quality. Using Xilinx® Vertex-2 FPGA technology, the logic gate count is only 4524, critical path delay is 8.104ns , output delay is only 22 clock cycles, & the maximum operational frequency is 127MHz.

Key words: , ,

Mostra/Nascondi contenuto.
1 CHAPTER 1 Introduction 1.1 Statement of the Problem In the past decade, there has been an explosive growth in the field of multimedia Communications, where digital video plays an important role. The advance in digitizing visual information has led to the rapid development of multimedia technology and applications due to the compatibility of digital video with other types of information such as text or voice. Digital video contains huge amount of data and despite the increases in processor speed and disc storage capacity, it is still necessary to represent it in a more concise format. The emergence of video compression techniques addresses this problem, making it feasible to store high quality video on a limited-storage disc or transmit it within the limited-bandwidth that today’s network can provide. It also drives the development of many widely used applications, such as video conferencing, Digital Versatile Disc (DVD), High Definition Television (HDTV) and so on. The compression of digital video is accomplished by a video CODEC, consisting of an encoder that compresses the original video signal and a decoder that reconstructs the original video based on the coded video sequence. Hence, for the real-time video application, video CODECs were implemented in specially designed hardware because coding and decoding is an extremely computationally complex process (requiring a large amount of calculations), and only dedicated hardware was capable of dealing with it. It can provide acceptable performance with benefits in terms of cost, flexibility and availability. Consequently, it is now widely used in video applications, such as video conferencing, video telephony, video streaming and mobile video phones. The performance of a hardware-only video CODEC may be limited by the amount of processing power available as well as, or rather than, the available transmission bandwidth. This is particularly true in a real-time video communication system and/or power-constrained system. In a desktop video conferencing system, the CODEC runs on a general-purpose PC and has to share processing resources with other applications. In a. mobile video handset, power consumption is closely related to processor utilization and it

International thesis/dissertation

Autore: Sadiq Ullah Khan Yousafzai Contatta »

Composta da 79 pagine.

 

Questa tesi ha raggiunto 416 click dal 03/03/2006.

Disponibile in PDF, la consultazione è esclusivamente in formato digitale.