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High Throughput Turbo Decoder for HSDPA

Turbo codes are of great interest since they are able to provide better performance than other known coding techniques. Moreover they are included in the UMTS standard.

In this thesis the design of a 3GPP compliant turbo decoder for HSDPA application is proposed. Various architectural trade-offs are analyzed and appropriate choices are made in order to achieve the high data rates required by the standard. In the end, the recursion level parallelized SW SMAP architecture with alpha approach has been implemented, together with a hardware interleaver able to generate the address required for the interleaving on-the-fly. The turbo decoder is also able to handle all the block lengths specified by 3GPP.

The developed architecture has been synthesized and the clock frequency is 100 MHz in UMC 0.13 CMOS process. The turbo decoder reaches a maximum data rate of 8.9 Mbits/s for a block length of 5114 bits at 100 MHz and with six iterations.

Mostra/Nascondi contenuto.
Chapter 1 Introduction 1.1 Motivation Turbo codes [1] were discovered in 1993, and since they appeared they have gener- ated a tremendous interest in the scientific community, due to near Shannon-limit performance. Thus it is not astonishing to find the turbo codes in the specification for UMTS. Implementing a turbo decoder is a challenging task, especially when high through- put is required. The goal of this project is the development of a high throughput turbo decoder for HSDPA applications able to handle all the block lengths specified by 3GPP. Having this aim in mind, several steps have been taken. The approach proposed here is optimizing both from an algorithmic and an architectural aspects. 1.2 Thesis organization The thesis is organized as follows: Chapter 2 introduces to the field of turbo cod- ing; Chapter 3 shows achievable optimizations from an algorithmic point of view; Chapter 4 discusses various architectural trade-offs regarding the SISO decoder unit and the interleaver implementation; Chapter 5 presents the turbo decoder design; Chapter 6 summarizes the achievement of this work.

International thesis/dissertation

Autore: Teo Cupaiuolo Contatta »

Composta da 84 pagine.

 

Questa tesi ha raggiunto 400 click dal 02/11/2006.

 

Consultata integralmente una volta.

Disponibile in PDF, la consultazione è esclusivamente in formato digitale.