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Assessment of Copper Interconnects

Enhancements in integrated circuits (IC) density and performance have fueled semiconductor industry and the resultant information revolution for over 40 years. The improvements in density (Moore’s Law) and performance has been achieved through evolutionary and revolutionary advances in the front end of the chip manufacturing line, where the circuit elements are fabricated, and the back end, where these elements are appropriately wired within the IC. Chip interconnections or interconnects, serve as global wiring, connecting circuits’ elements and distributing power.
To incorporate and accommodate the improvements such as decreased feature size, increased device speed, and more integrate designs, research in the back-end-of-the-line (BEOL) has become equally important as developing the front-end-of-line (FEOL).
Advances in interconnect technology have one important milestone in the planar multilevel metallization architecture, where planarity is achieved by the extensive use of Chemical Mechanical Polishing – CMP. Planar wiring has improved structural integrity and facilitated continuous improvements in wiring pitch, number of metal layers, and design features, such as stacked vias and local interconnections. Aluminum has been replaced with electrochemically deposited copper, and, consequently, the industry-standard subtractive metal etching process has been replaced by a damascene process: wire patterns (trenches and via holes) are first etched in an insulator, then filled with copper, and excess copper is removed by chemical mechanical planarization. In a dual damascene process both via and trench structures are filled in a single step.
Copper interconnects fabricated by a dual damascene process offer advantages of performance, cost, reliability over existing aluminum wiring process. Performance is gained because the resistivity of copper is approximately 40% lower than that of aluminum, so copper wires exhibit approximately 40% lower RC delay than aluminum wires of the same cross section. Moreover, the dual damascene approach, compared with single damascene, provides lower via resistance reducing the number of interfaces in the vias. Cost reduction comes from eliminating some process steps and simplifying other process steps in the dual-damascene process. Reliability is improved because the electrochemical deposited copper, when compared with aluminum, exhibit far less electromigration and far less stress migration.

The present work on copper interconnects resulted from an internship carried out at the Interuniversity MicroElectronics Center – IMEC -, Leuven, Belgium, a challenging international leading edge research center. The subject described in this thesis covers most of the work that I carried out from the beginning of August to the second half of November, 2005.
Four main topics were covered and they have lead to the four-chapter structure of this thesis. A brief introduction is present, too. It gives a general overview of the main process steps in the interconnect technology.
“Chapter 1: Interconnect RC delay simulations” describes an attempt to model interconnect RC delay starting from geometric considerations by comparing the simulated delay with the measured one, to identify the impact of several assumptions on the RC delay extraction accuracy. Capacitance simulations were carried out using Synopsys Raphael™.
“Chapter 2: Within-die and within-wafer interconnect R and C systematic variability” aims at understanding systematic interconnect resistance and capacitance variability both at die and wafer level. Variability at die level is dominated by layout pattern dependencies while variability at wafer level is related to process signatures.
“Chapter 3: Response Surface Modeling of interconnect capacitance” tries to correlate electrical capacitance and interconnect physical dimensions, i.e., how small variations in the interconnect cross-sectional dimensions lead to changes in the interconnect capacitance.
“Chapter 4: X-ray fluorescence assessment of interconnect thickness” aims at understanding XRF line scan measurements over patterned regions through simulations.
Two small appendices complement these four chapters.
“Appendix I: Evaluation of interconnect resistivity” describes the steps used to measure copper interconnect resistivity.
“Appendix II: XRF line-scan simulator “Deo Gratias” Matlab® code” simply contains the Matlab® code of the XRF line-scan simulator used in the study described in chapter 4.

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Chapter 3 Response Surface Modeling of interconnect capacitance « New ideas pass through three periods: 1. It can't be done. 2. It probably can be done, but it's not worth doing. 3. I knew it was a good idea all along! » − Arthur Charles Clarke (1977 - ). 3.1 Introduction In chapter 1, we found that even using the actual cross-sectional shape and dimensions, we were not able to match the measured capacitance. If we assume that Raphael TM field solver is 100% accurate, there could be several explanations for this problem. For example, the cross section dimensions are not constant and slightly change along the meander-fork length. Consequently, it is not completely correct to measure the section from one or two FIB/TEM images and associate it to the entire meander-fork. By the work described in this chapter, I want to understand the correlation between electrical capacitance and interconnect physical dimensions, i.e., how small variations in interconnect cross-sectional dimensions lead to changes in interconnect capacitance. I want to go even a step further linking the distribution of measured electrical capacitance over the wafer (chapter 2) to the distribution of interconnect cross-sectional dimensions. To this purpose, I used the Response Surface Modeling – RSM –, as implemented in Noesis Solutions NV OPTIMUS v. 5.1 software, and I built a model for the

Tesi di Master

Autore: Gerardo Bottiglieri Contatta »

Composta da 151 pagine.


Questa tesi ha raggiunto 356 click dal 24/05/2006.

Disponibile in PDF, la consultazione è esclusivamente in formato digitale.